Technical Director Memory Controller Architect (San Jose)
Rambus is looking for Technical Director Memory Controller Architect (San Jose) in San Jose, CA.
This local job opportunity with ID 3770113221 is live since 2026-08-01 10:50:39.
Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Memory Controller Architect and Technical Director to join our Silicon IP (SIP) team. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. This full‑time leadership position reports to the VP of Engineering. As an individual‑contributor, you will architect high‑performance, cutting‑edge memory controllers for data centers and AI applications. The role is located in San Jose, California or Hillsboro, Oregon, US, with a flexible, hybrid work model encouraging at least three days onsite per week. Responsibilities Own the architecture specification for Rambus memory controllers Work closely with product management, product marketing, technical field organization and customers to understand feature priorities and market needs Collaborate with logic design, verification and physical design teams to define implementation‑friendly, high‑performance and PPA‑optimized products and realistic timelines Actively drive technical reviews including implementation review, verification review, PRD/ERD review Represent the Rambus SIP team at JEDEC standards body Work closely with system modeling team to explore and finalize next‑generation architectures Collaborate with Rambus Labs research team to incorporate innovative and differentiated features to establish clear leadership Protect Rambus innovations through patent disclosures Serve as the technical expert to provide architectural solutions to customers to grow Rambus SIP memory business Evangelize Rambus memory controller products through technical publications and industry events Empower field teams through product training in collaboration with marketing and product management teams Qualifications BS/MS with 20 years’ experience in semiconductor industry, with at least 10 years on memory logic design and/or architecture. IP experience is preferred Hands‑on experience with RTL coding, logic design, physical design and DV techniques Knowledge of HBM, LPDDR and AXI protocols and controllers. GDDR and CHI protocol knowledge will be a plus Knowledge of front‑end ASIC development flow and best practices Knowledge of system architecture for HPC and AI systems, including impact to memory controller architecture Strong verbal and written communication skills and the ability to work in a fast‑paced environment Excellent soft skills and collaborative mindset to work with cross‑functional teams Ability to make timely decisions based on available data Technical presales experience is desirable This role involves deep technical skills and domain expertise while also requiring excellent soft skills Ability to travel to Rambus sites as well as customer locations as required Benefits and Compensation Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time‑off program, and gym membership. The U.S. salary range for this full‑time position is $189,700 to $352,300. Salary is determined by role, level, location, skills, experience and market conditions. Equal Employment Opportunity Rambus is a proud Equal Employment Opportunity and affirmative action employer. The company does not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, gender identity, age, veteran status, disability, genetic information, or any other legally protected characteristic. Rambus provides reasonable accommodations for qualified individuals with disabilities and disabled veterans during the job application process. J-18808-Ljbffr5c143e31-5e48-4549-b638-05792d185386
Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Memory Controller Architect and Technical Director to join our Silicon IP (SIP) team. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. This full‑time leadership position reports to the VP of Engineering. As an individual‑contributor, you will architect high‑performance, cutting‑edge memory controllers for data centers and AI applications. The role is located in San Jose, California or Hillsboro, Oregon, US, with a flexible, hybrid work model encouraging at least three days onsite per week. Responsibilities Own the architecture specification for Rambus memory controllers Work closely with product management, product marketing, technical field organization and customers to understand feature priorities and market needs Collaborate with logic design, verification and physical design teams to define implementation‑friendly, high‑performance and PPA‑optimized products and realistic timelines Actively drive technical reviews including implementation review, verification review, PRD/ERD review Represent the Rambus SIP team at JEDEC standards body Work closely with system modeling team to explore and finalize next‑generation architectures Collaborate with Rambus Labs research team to incorporate innovative and differentiated features to establish clear leadership Protect Rambus innovations through patent disclosures Serve as the technical expert to provide architectural solutions to customers to grow Rambus SIP memory business Evangelize Rambus memory controller products through technical publications and industry events Empower field teams through product training in collaboration with marketing and product management teams Qualifications BS/MS with 20 years’ experience in semiconductor industry, with at least 10 years on memory logic design and/or architecture. IP experience is preferred Hands‑on experience with RTL coding, logic design, physical design and DV techniques Knowledge of HBM, LPDDR and AXI protocols and controllers. GDDR and CHI protocol knowledge will be a plus Knowledge of front‑end ASIC development flow and best practices Knowledge of system architecture for HPC and AI systems, including impact to memory controller architecture Strong verbal and written communication skills and the ability to work in a fast‑paced environment Excellent soft skills and collaborative mindset to work with cross‑functional teams Ability to make timely decisions based on available data Technical presales experience is desirable This role involves deep technical skills and domain expertise while also requiring excellent soft skills Ability to travel to Rambus sites as well as customer locations as required Benefits and Compensation Rambus offers a competitive compensation package including base salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time‑off program, and gym membership. The U.S. salary range for this full‑time position is $189,700 to $352,300. Salary is determined by role, level, location, skills, experience and market conditions. Equal Employment Opportunity Rambus is a proud Equal Employment Opportunity and affirmative action employer. The company does not discriminate on the basis of race, religion, color, national origin, sex, sexual orientation, gender identity, age, veteran status, disability, genetic information, or any other legally protected characteristic. Rambus provides reasonable accommodations for qualified individuals with disabilities and disabled veterans during the job application process. J-18808-Ljbffr5c143e31-5e48-4549-b638-05792d185386